I/O pull-down devices have regularly been used to protect I/O logic circuits from electrostatic discharge (ESD). One such I/O pull-down device 100 is shown in FIG. 1. Device 100 comprises a P-well or P-type substrate or body 110 having P+ taps or contacts 120, a polysilicon gate 140 on the substrate and insulated therefrom by gate oxide 145, heavily doped N-type source and drain regions 150, 160, and N-type lightly doped drain (LDD) regions 155, 165 extending toward each other in the substrate from the source and drain regions. A parasitic NPN bipolar transistor is formed in this device in which the source and drain regions 150, 160 are the emitter and collector of the transistor and the P-well or substrate 110 is the base. The structure of a typical I/O logic device is similar to that of device 100 and is typically formed in the same integrated circuit as I/O pull-down device 100.
FIG. 2 is a top view of an implementation of device 100 of FIG. 1. Device 100 is formed in a portion of a semiconductor substrate 205. A P-well 210 is formed in that portion and electrical connection to the P-well is made through P+ well taps 220. Illustratively, the P-well tap extends around the entire periphery of P-well 210. An NMOS transistor is formed in the P-well having a plurality of gate fingers 240 and N+ source/drain regions 250 on both sides of the gate fingers. While not shown in FIG. 2, N-type lightly doped drain (LDD) regions extend toward each other from the source/drain regions 250 on both sides of each gate finger 240.
FIG. 3 depicts the use of device 100 in a typical input/output circuit 300. Circuit 300 comprises pull-down device 100 connected between an I/O pad 392 and ground VSSIO. Pull-down device protects from ESD events one or more logic circuits 302 containing devices that are similar to device 100 and connected between I/O pad 392 and ground. Illustratively, a first ballast resistor 362 is connected between drain 360 of pull-down device 100 and the I/O pad and a second ballast resistor 352 is connected between source 350 of device 100 and ground. P-well or P-type substrate or body 110 of device 100 is connected to ground. Ballast resistors 352, 362 are used to provide a more uniform current distribution through device 100. Alternatively, a salicide block could be used. The resistance of the P-type body is represented in the schematic by resistor 312. A diode 394 is connected between I/O pad 392 and ground with its cathode connected to the I/O pad and its anode connected to ground. Diode 394 is used to discharge negative voltage electrostatic events.
Since both the I/O pull-down device and the circuitry that it is intended to protect are in general formed at the same time through the same implants, the breakdown voltage of the I/O pull-down device and that of any other NMOS device connected to the pad are substantially the same. In the absence of an input resistance to isolate the NMOS I/O pull-down device from the circuits to be protected, some layout techniques can be adopted to prevent competitive triggering such as locating the p+taps of the I/O pull down device at a larger distance from its active area compared to the distance between the circuits to be protected and their taps. However, capacitive coupling of sensitive nodes to the pad potential or specific topologies can still create the potential of competitive triggering unless the triggering voltage of the I/O pull down device is lowered significantly.
Various methods are used for reducing the trigger voltage of the I/O pull-down transistor. In U.S. Pat. No. 6,882,009 of M. Ker et al., P-type pocket implants are used next to the source/drain regions. However, since the P-type pocket implants are used throughout the circuit, this reduces the trigger voltage of both the pull-down transistors and the logic transistors. As a result, the I/O pull-down transistor may not be able to protect the I/O logic circuit. In addition, the P-type pocket implant can degrade the transistor performance by increasing its junction capacitance, and thereby reducing its speed, and can increase the transistor leakage. In M. Ker et al., “ESD Implantation for On-Chip ESD Protection with Layout Consideration in 0.18 um Salicided CMOS Technology,” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 2, pp. 328-337 (May 2005), a P-type ESD implant is located vertically under the source-drain area. This, however, significantly increases the junction capacitance and affects the transistor performance. It also increases the transistor leakage.
In the above-referenced application Ser. No. 11/185,609 which is incorporated herein by reference, an ESD protection device is disclosed in which a P-type region is formed underneath a portion of each N-type LDD region so that a P-N junction is formed with the drain/source region. In the embodiment of FIG. 2 of application Ser. No. 11/185, 609, the location of the P-type region and therefore the location of the P-N junction is indicated generally by the dashed rectangle 280. The rectangular region 280 is shown to cover the center area of the transistors for illustrative purposes, although it can be anywhere in the transistors. Preferably, the width W of the rectangular region 280 is approximately 25% of the width WLDD of an LDD region although greater widths can be used.